FIG. 1 is a schematic diagram of an array 100 of conventional flash memory cells (flash cells) detailed in U.S. Pat. Nos. 5,357,465 and 5,222,040. Array 100 includes flash cells 110-113, word lines 101-102, common source line 103, and drain bit lines 105-106, as illustrated.
In general, a non-volatile flash memory transistor (e.g., flash cell 110) includes a floating gate that can be programmed to store either a negative charge or a neutral charge. The amount of charge stored on the floating gate affects the threshold voltage of the flash cell. The threshold voltage of a flash cell is that voltage at which the flash memory transistor turns on, allowing full current to flow. When storing a negative charge, a flash cell is said to be in an erased state. When storing a neutral charge, a flash cell is said to be in a programmed state. When a flash cell is in the erased state, the negative charge stored on the floating gate prevents the flash cell from turning on at the low voltages used for reading the flash cell during a read operation. Therefore the erased flash cell is said to be in a high threshold state. When a flash cell is in the programmed state, the neutral charge stored on the floating gate allows the flash cell to be controlled by the voltage applied to the control gate of the flash cell. Therefore the programmed flash cell is said to be in a low threshold state.
FIG. 2 is a cross-sectional view of flash cell 110 of array 100. Flash cell 110 includes p-substrate 160, n-well 170, n-well contact 171, p-well 180, p-well contact 181, source 120, drain 130, tunnel oxide region 153, floating gate 154, isolation material 155, and control gate 156. Control gate 156 is conventionally word line 101, thereby coupling flash cell 110 to other flash cells in the array. The entire array of flash cells is fabricated within p-well 180, n-well 170, and substrate 160. The charge on floating gate 154 determines the threshold voltage of and identifies the state of flash cell 110.
FIG. 3 is a table describing the voltages for operating array 100. Array 100 can perform program, program inhibit erase, and read operations, as illustrated.
During the program mode, relatively high voltages are applied across the control gate (0 Volt) and the drain (+5 Volts) of flash cells on the non-selected word line and the selected drain bit line. These high voltages can result in drain disturb in erased cells. Drain disturb occurs when an electrical field is strong enough to cause the floating gate to experience a charge loss due to electron tunneling from the floating gate to the drain. It is therefore an object of the present invention to lessen the drain disturb in a flash array.
Minute variations in the size of the elements of a transistor can occur during transistor formation. As a result, some flash cells can have slightly thinner or thicker tunnel oxide regions. Electrons tunnel more easily through flash cells having thinner tunnel oxide regions during a program operation. As a result, flash cells having a thinner tunnel oxide region are less negatively charged during a program operation. These flash cells therefore have a lower threshold voltage than flash cells with thicker tunnel oxide regions. In some cases, the floating gate of a flash cell can lose enough charge to cause the threshold voltage of the flash cell to go negative. When this happens, a grounding voltage applied to the control gate does not turn off the flash cell. Cells with negative threshold voltages are called over-programmed cells. To conventionally prevent non-selected cells from turning on, a voltage more negative than the negative threshold voltage of the most over-programmed cell must be applied to each non-selected cell in the array. This large negative voltage causes a large voltage to be applied across the control gates and the drains of the non-selected flash cells in the array. This voltage can disturb the amount of charge on the floating gate of these flash cells under certain conditions. It is therefore another objective of the present invention to find a better way to prevent turn-on of non-selected, over-programmed cells.
A flash cell is erased by applying the voltages listed in FIG. 3 to the array for a given period of time. Erasing is performed in blanket mode, meaning that all cells in an array are erased simultaneously. An array of cells is erased by applying a large positive voltage (e.g., 20.0 Volts) to each control gate, and grounding each source, drain, and substrate. Under these conditions, electrons tunnel from the substrate to the floating gate. As a result, after erasing, all cells should be in a high threshold voltage state.
A row of flash cells is read by applying the voltages listed in FIG. 3 to the array for a given period of time.
The junction of the drain region and a well region of a flash cell is called a drain junction. For example, the drain junction of flash cell 100 is located between the drain region (e.g., drain 130) and the p-well (e.g., p-well 180). The drain junction of a flash cell is designed to provide efficient F-N tunneling between the floating gate and the drain during a program operation. This is accomplished by implanting a more heavily doped (e.g., N+) region that is under-lapping the floating gate. As a result of the under-lapping, a tunneling region is created. Due to this sensitivity, applying a positive voltage to the drain may cause F-N tunneling induced read disturb in non-selected erased cells in the array. Read disturb occurs when the charge on a floating gate is altered by a read operation. In this case, read disturb occurs when an electrical field is strong enough to cause the floating gate to experience a charge loss due to electron tunneling from the floating gate to the drain. The floating gate is therefore less negatively charged after the read operation, and thus the threshold voltage of the cell is lowered. It is therefore an object of the present invention to lessen the read disturb occurring to non-selected, erased cells.
As an additional result of the under-lap of the heavily doped region with the floating gate, applying a positive voltage to the drain also causes hot electron induced read disturb if the selected cell is in a programmed state. In this case, the read disturb occurs when an electrical field is strong enough to cause the electrons flowing between the source and the drain during the read operation to gain enough energy to jump through the tunnel oxide layer into the floating gate. As a result, the floating gate contains additional charge after the occurrence of the read disturb. It is therefore another object of the present invention to lessen the read disturb that can occur in selected, programmed cells during a read operation.
Each cell in array 100 (FIG. 1) has one metal line and one diffusion line. Drain bit lines 105 and 106 are metal bit lines, and common source line 103 is a diffusion line. Diffusion lines inherently have large leakage current as well as large resistance and capacitance delays. As a result, the conduction performance of diffusion lines essentially act as an efficient connector coupled to a resistor and a capacitor. The added resistance and capacitance on the line is called RC delay. The RC delay of the diffusion line delays current along the line, thus delaying accesses to memory array 100. It is therefore another object of the present invention to increase the access speed to a flash memory array.
FIG. 4 is a layout diagram containing flash memory array 100. Similar elements in FIGS. 1, 2, and 4 are labeled with similar reference numbers. The layout diagram of flash cell array 100 therefore contains word lines 101-102, common source line 103, drain bit lines 105-106, drain regions 130-133, and source regions 120-121.
FIG. 5A is a schematic diagram of another conventional array 500 of flash cells as described in U.S. Pat. No. 5,592,415. Array 500 includes flash cells 510-513, word lines 504-505, drain bit lines 506-507, and source bit lines 508-509. Bit lines 506-509 are buried diffusion lines.
FIG. 5B is an equivalent circuit of flash memory array 500. Each of buried diffusion lines 506-509 are represented as an efficient conducting line coupled to a resistor and a capacitor. As noted above, buried diffusion lines have an inherent RC delay. The amount of RC delay in an array is directly proportional to the length of the buried diffusion line. This RC delay makes it difficult to use large flash memory arrays connected by buried diffusion lines efficiently in high density flash memory. The delays caused by the length of the buried diffusion lines in large arrays are incompatible with the speed required in high density flash memory applications. To reduce the RC delay of the array, U.S. Pat. No. 5,592,415 provides many small arrays. The typical size of these small arrays is 32 by 32 sectors, where a sector is a block of flash cells. The smaller array has proportionally shorter buried diffusion lines, with proportionally smaller RC delay. However, each of the 32.times.32 sectors must be interconnected to function as a large array. The additional interconnection makes this design more complicated than the conventional flash memory array of FIG. 1.
FIG. 5C is a table describing the voltages for operating flash array 500. Flash array 500 is programmed, erased, and read in a manner similar to array 100. Buried diffusion drain bit lines 506-507 inherently provide a large drain junction area. The amount of leakage current during programming is proportional to the size of the drain junction area. As a result, flash array 500 experiences a large leakage current during a program operation. It is therefore another object of the present invention to lessen the drain leakage current during programming.
Flash array 500 is read by applying a voltage of 3.3 Volts to the selected word line (e.g., WL.sub.1), a pre-determined positive voltage (e.g., 2.0 Volts) to the selected drain bit line (e.g., BL.sub.1), and a grounding voltage of 0 volts to both the selected source bit line (e.g., SL.sub.1) and the substrate. Under these circumstances, a programmed cell (e.g., flash cell 510) conducts current and an erased cell (e.g., flash cell 511) does not conduct current. Sense amplifiers coupled with drain bit lines 506-507 sense the voltage change on drain bit lines 506-507.
However, as mentioned above, the drain junction is designed to have efficient F-N tunneling. Therefore, as with the circuit of FIG. 1, applying a positive voltage to the drain also causes hot electron induced read disturb if the selected cell is in a programmed state. This hot electron induced read disturb causes the threshold voltage of the affected programmed flash cell to increase. As noted above, it is another objective of the present invention to lessen the read disturb of selected, programmed cells during a read operation.
Additionally, the manufacturing process for forming buried diffusion lines 506-509 is very complicated. This process is further complicated by the need to form many small 32.times.32 sectors rather than one large array. It is therefore another object of the present invention to provide a flash memory array using a relatively simple manufacturing process.
FIG. 6 is a layout diagram of flash cell array 500. Similar elements in FIGS. 5A, 5B, and 6 are labeled similarly. The layout diagram of flash cell array 500 therefore contains word lines 504-505, (diffusion) source bit lines 508-509, (diffusion) drain bit lines 506-507, and flash cells 510-513. Also included are isolation material 42, drain select transistor gate 45, additional word lines 47, source select transistor gate 49, and common source lines 50. Note that the drain select transistor gate 45 is located at the top of the array, and the source select transistor gate 49 is located at the bottom of the array. The distance between select transistor gates 45 and 49 impairs the ability to exchange the associated control lines.